SAF7730HV/N336

Product Summary

The SAF7730HV/N336 is a 9-bit video input processor. The SAF7730HV/N336 is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N and SECAM), a brightness, contrast and saturation control circuit, a multi-standard VBI data slicer and a 27 MHz VBI data bypass. The applications of the SAF7730HV/N336 include Notebook (low power consumption), PCMCIA card application, AGP based graphics cards, Image processing, video phone applications, Intercast and PC teletext applications, Security applications.

Parametrics

SAF7730HV/N336 absolute maximum ratings: (1)VDDD digital supply voltage: 3.0V to 3.6V; (2)VDDA analog supply voltage: 3.1V to 3.5V; (3)Tamb operating ambient temperature -40℃ to 85℃; (4)PA+D analog and digital power dissipation: 0.4W.

Features

SAF7730HV/N336 features: (1)Four analog inputs, internal analog source selectors; (2)Two analog preprocessing channels in differential CMOS style for best S/N-performance; (3)Fully programmable static gain or automatic gain control for the selected CVBS or Y/C channel; (4)Switchable white peak control; (5)Two built-in analog anti-aliasing filters Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the VPO-port via I2C-bus control; (6)On-chip clock generator; (7)Line-locked system clock frequencies; (8)Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection; (9)Requires only one crystal (24.576 MHz) for all standards; (10)Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards; (11)Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM; (12)User programmable luminance peaking or aperture correction; (13)Cross-colour reduction for NTSC by chrominance comb filtering; (14)PAL delay line for correcting PAL phase errors; (15)Brightness Contrast Saturation (BCS) and hue control on-chip; (16)Real-time status information output (RTCO); (17)Two multi functional real-time output pins controlled by I2C-bus; (18)Multi-standard VBI-data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc. Standard ITU 656 YUV 4 : 2 : 2 format (8-bit) on VPO output bus; (19)Enhanced ITU 656 output format on VPO output bus containing: active video, raw CVBS data for INTERCAST applications (27 MHz data rate), decoded VBI data; (20)Boundary scan test circuit complies with the "IEEE Std. 1149.b1 - 1994" (ID-Code = 1 7113 02B); (21)I2C-bus controlled (full read-back ability by an external controller, bit rate up to 400 kbits/s); (22)Low power (＜0.5W), low voltage (3.3V), small package (QFP44); (23)Power saving mode by chip enable input; (24)Detection of copy protected input signals according to the macro vision standard. It can be used to prevent unauthorized recording of pay-TV or video tape signals.

Diagrams